Want to know what the next 10 years of Moore’s Law is going to look like? Maybe the next 15? The Belgium-based nanotech research institution Imec revealed its updated roadmap this week at its annual technology forum, ITF, and it points to a challenging road ahead for chip manufacturers.
The next evolution in CMOS transistors, the kind in almost all chips on the planet, will be the complementary field-effect transistor (CFET), and Imec predicts its commercial introduction will begin around 2033.
Further out, Imec expects another transition in transistor technology, this one driven more by power reduction than squeezing more devices onto a chip. In 2041, chipmakers may replace the main silicon part of the transistor, the channel region, with two-dimensional semiconductors. These are materials, such as molybdenum disulfide, that act as semiconductors even though they are only a single atomic layer thick.
Yes, 15 years is a very long time in an industry as fast moving as semiconductors. Imec’s projections extend so far out because of the role of its research in the semiconductor industry, says Paul Heremans, the organization’s chief technology officer. “Our research programs do de-risking of technology options,” he says. That is, they explore the costs and benefits of different choices with the aim of narrowing the field for chipmakers. “We have to be really well ahead of the time of the introduction of such technology into a real product, because after our de-risking work, there is still a lot of engineering and development work to get these technologies into production,” he says.
With de-risking as the goal, much of Imec’s focus right now is on what’s coming in 2033, and that’s the CFET.
So Many Choices for CFETs
The CFET is an attempt to build two transistors in the space of one. The CMOS logic that’s run computing for decades relies on two types of transistors—one called PMOS (p-channel metal-oxide semiconductor), the other NMOS (negative-channel metal-oxide semiconductor). They function so that the same input signal will cause one to switch on and the other to switch off, which helps foster relatively efficient operation. Today they are built in pairs side by side. CFETs would stack them on top of each other, which would be as good as halving the area of some circuits, according to proponents.
The likely path to the CFET builds both transistors at once, instead of one after another or building them on separate wafers and then somehow fusing them together. That starts by depositing multiple alternating layers of silicon and silicon-germanium onto a silicon wafer. After trenches and other features are carved through those layers, etchants that destroy silicon-germanium (but not silicon) are deployed to leave a set of suspended stack, nanometers-thick silicon ribbons. The top set of those ribbons, called nanosheets, become the PMOS transistor, and the bottom set becomes the NMOS, or vice versa.
The world’s largest chipmakers—Intel, Samsung, and TSMC—are now working to make CFET-based chips manufacturable. Each of them have constructed prototype CFET chips. TSMC used its devices to build a super compact memory cell and a key test circuit called a ring oscillator, company engineers announced last December at the IEEE International Electron Devices Meeting. In June, at the IEEE VLSI Symposium, Samsung will detail a CFET that is simultaneously the smallest yet and made with the most layers of nanosheets (six in total).
Nevertheless, how best to make CFETs is far from settled. “It is very clear that there are many versions still open,” Heremans says. For example, Imec has been developing new ways to better electrically separate the top and bottom transistor from each other, so they can work independently. The process that would make that possible is complicated. The silicon and silicon-germanium layers that will become the top transistor would be made on an entirely different silicon wafer. The two wafers are then bonded together in a way that leaves only the silicon and silicon-germanium layers from the top wafer attached to the bottom wafer. The process also leaves an extra layer of insulation between the material from the top wafer and the bottom wafer, providing the needed electrical isolation.
As difficult as that might seem, it could also help solve a mismatch in the speed of charge through PMOS and NMOS. Today’s chips use silicon wafers that are sliced along a crystal plane that favors conduction in NMOS. But if the PMOS layers are made on a separate wafer, that wafer could be cut to favor those devices. Intel is testing that scheme right now and will report the results of that work in June at the IEEE VLSI Symposium.
Imec expects CFETs to follow a similar evolution to other recent technology introductions, such as the FinFET (fin field-effect transistor) 15 years ago, and the nanosheet transistor, which is entering commercial products now. That is, an initial launch, then an effort to boost the density and performance, and finally a push to squeeze a bit more performance or power efficiency out of the dense version.
After that, probably around 2041, Imec expects industry to swap the silicon in CFETs for something new, such as one or more types of 2D semiconductors. Unlike with the move to CFETs, 2D semiconductors would mostly be about improving power consumption.
“The general goal of continuing the roadmap is, of course, to propose technologies that will increase the operation per watt that you can generate,” Heremans says. In advanced chips, a small reduction in voltage has an outsized effect on reducing power.
That’s where 2D could come in. 2D semiconductors are less than a nanometer thick, compared to the 3 nanometers of a future silicon nanosheet, Heremans points out. The transistor’s gate, which wraps around the channel region, could therefore use less voltage to control the flow of current through such a thin structure in comparison with the thicker silicon nanosheet. 2D CFETs could get a further efficiency boost if industry selects a semiconductor through which charge flows faster, Heremans suggests.
If CFETs arrive when Imec says they will, they’ll drop into an industry that’s already thinking in 3D. Intel has already moved power-delivering interconnects beneath the layer of silicon transistors on a chip, and with the CFET’s complicated connections, some data signals may have to move there as well.
Just as important, by 2033, chip companies will have more than a decade of experience stacking one chip atop another to increase the total amount of silicon in a processor. For example, in an AMD MI300 GPU, “compute tiles” made using the most advanced processes are stacked atop another die made using an older process that handles the GPU’s memory and communications.
The vertical connections in the AMD chip can be separated by as little as 9 micrometers. And that spacing is decreasing rapidly. “Today our most advanced wafer-to-wafer bonding technologies [in development] allow a pitch of about 200 nanometers,” Heremans says. “That means over 1 millimeter square, we’re talking about 25 million interconnects.”
That kind of density means that designers can start to build logic circuits in 3D dies,” Heremans says. Such an ability would lead to an evolution in chip design that Imec calls CMOS 2.0. In that scheme, not only can multiple chips made with different technologies be stacked together but individual chips can be made by fusing together layers of transistors, each optimized for a specific function such as memory density or driving current. “That gives you an enormous boost in what you can expect from this kind of fused chip,” he says.
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