Records Fall for 3D Chip Tech

As transistor sizes shrink to their atomic limits, computing demands are only growing. Sending chips to the third dimension is the future: Chips stacked on other chips can get more work done in the same footprint, saving time and energy. A 3D chipmaking technology called hybrid bonding is leading the charge in such efforts. Last month, two research teams used the tech to make hundreds of thousands more connections per millimeter than were previously possible, setting new records.

Presented at the IEEE Electronic Components and Technology Conference (ECTC) in Orlando, both results drastically reduced the bond pitch, the distances between the copper connections that bridge hybrid-bonded chips. The smaller the pitches, the more connections can fit in a package, and the more efficiently computing can get done.

“When we are talking about hybrid bonding at finer pitches, we can directly think about lowering the power consumption, having denser interconnects, and actually improving the communication between devices,” says Melissa Najem, a research engineer at the French microelectronics laboratory CEA-Leti. “This is actually extremely important to meet the rapidly growing demands for next generation semiconductor devices, such as for AI, for high performance computing, for high-bandwidth memory.”

Hybrid bonding places pads of copper and insulation on the faces of two or more chips, squishes them together, and adds heat so that the copper expands and joins, creating an electrical connection. The joining pads must be precisely aligned to within less than a micrometer for the process to work.

“A lot of applications are here just waiting for the improvement of die-to-wafer hybrid bonding"—Melissa Najem, CEA-Leti

The two ECTC records take different approaches to hybrid bonding. Belgium-based semiconductor research center Imec presented a record for hybrid bonding whole wafers of chips. This wafer-to-wafer approach (W2W) is useful for memory and logic applications, but is less flexible for other uses as it requires uniformity of the wafers. In collaboration with chip manufacturing equipment maker EV Group, Imec got W2W pitches down to 200 nanometers from a previous low of 250 nm announced last year.

CEA-Leti’s record involves a die-to-wafer (D2W) approach, which places individual chips, also called dies, on a full wafer of chips (think adding pepperoni to a pizza). This method lets chipmakers mix and match the sizes and functionalities of the stacked chips. The researchers presented D2W pitches at 1 μm—yes, five times bulkier than the W2W milestone, but a 50 percent reduction from the last published record of 2 μm. A 1-μm pitch means a million connections per square millimeter, or four times as many as before.

Wafer-to-wafer and die-to-wafer hybrid bonding

W2W hybrid bonding is the more straightforward method of the two: Connections require an alignment accuracy down to a minuscule 50 nm, but the uniformity of the silicon wafers makes the painstaking job a bit easier. Achieving smaller W2W pitches is mostly hung up on smoothing connection points as much as possible.

To flatten surfaces sufficiently for the 200 nm record, researchers improved a process called chemical mechanical polishing (CMP) ], says Imec program director of 3D system integration Zsolt Tokei. They combined this effort with improvements to wafer alignment and copper pad design.

Srinidhi Ramamoorthy, a heterogeneous integration engineer at Applied Materials who was not involved in either breakthrough, notes that some research institutes have made wafers with W2W pitches below 200 nm, but that these records were not published alongside both electrical testing and reliability data. Without that information, she says, those numbers are “not the final pitch.”

For the D2W approach, the 1 μm record depended more on alignment accuracy than smoothness: Imagine having to drop a pepperoni on a pizza in a microscopically precise place, over and over. Najem says that CEA-Leti’s record was met by fine-turning the alignment process, alongside improved CMP.

The type of die CEA-Leti bonded to their wafer was a test vehicle, which records information to evaluate electrical connections. Najem says the test vehicle got data for multiple pitch levels, and while pitches above 1 μm had good electrical yields about 90 percent of the time, that number decreased to 22 percent for 1 μm.

Improving that yield is part of the next step for research, Najem says. “It’s important to have better devices, but it’s always better to know how efficiently they will be interconnected,” she says.

Hybrid bonding’s importance to Huawei

Blocked by U.S. export controls from using advanced chipmaking tools, Huawei is turning to 3D chip stacking to keep increasing transistor density. Last month the company presented their own hybrid bonding milestone at the IEEE International Symposium on Circuits and Systems in Shanghai. As part of a plan to catch up with global chipmakers, Huawei president He Tingbo said the company had implemented a hybrid bonding pitch of 1.5 μm in its coming generation of Kirin processors. This could mark a significant step toward parity with global chipmakers, but the method Huawei used is unclear.

Experts are hesitant to speculate on how Huawei achieved the pitch, but they don’t venture into skepticism. “Connections can be realized in different ways,” Imec’s Tokei says. “It’s never that there is only one way to do things.”

The next steps for the global chip industry are clear: Get the current research milestones out of the lab and continue hitting new milestones. Gabriela Pereira, a senior semiconductor packaging technology and market analyst at Yole Group, says mass production pitches are still at 6–9 µm for D2W and 1–2 µm for W2W. She says the challenges that make research milestones difficult, such as alignment and smoothing, hold back mass production, because mass production requires speed and replicability.

Pereira adds that the industry may end up throwing more weight behind D2W over W2W tech, because it offers more flexible uses. For researchers like Najem, the sentiment is the same.

“A lot of applications are here just waiting for the improvement of die-to-wafer hybrid bonding,” Najem says.