Junctionless Transistors Show a New Path to 3D Chips

Chipmakers are struggling to shrink the amount of area a transistor takes up, so researchers are trying to build layers of devices on top of each other. However, many experimental 3-D chips rely on exotic materials and perform poorly compared with regular silicon devices. But researchers at the University of Illinois Urbana-Champaign have found a new way to build 3D circuits from silicon. The secret is a process that lets them roll multiple layers of nanometers-thin silicon onto a wafer at relatively low temperatures.

Today’s 3-D microchips, such as the AMD MI300 series, stack prefabricated layers on top of each other and connect them with the help of metal pillars known as through-silicon vias. However, the challenge of properly aligning the connections between these layers limits how many links can be made and therefore how useful 3D stacking can be.

In contrast, in monolithic 3-D chips, layers of devices are fabricated directly on top of each other. This enables alignment of these layers with nanometer-scale precision, and orders of magnitude denser connectivity than today’s 3-D chips.

However, experimental monolithic 3-D chips require transistors and other devices in the upper layers to be fabricated at 400 degrees C or less to preserve the wiring that connects their components together. Such 3-D chips have been made using a variety of materials, but their performance and reliability all proved much worse than the metal–oxide–semiconductor field-effect transistors (MOSFETs) found in virtually all conventional microchips, erasing most of the gains offered by a monolithic 3-D design.

Now scientists have created monolithic 3-D chips from silicon at less than 200℃. “For years, people assumed monolithic 3D would require exotic new materials such as carbon nanotubes,metal oxide semiconductors, or 2D semiconductors,“ says Qing Cao, an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign. “Demonstrating that silicon can do the job means this technology can plug directly into existing manufacturing ecosystems, which dramatically accelerates its path toward real impact.”

Low-temperature junctionless transistors

Instead of the MOSFETs used in most chips, the new 3D chips rely on junctionless transistors. Regular MOSFETs are made using both n-type semiconductors, which are doped to contain an excess of electrons, and p-type semiconductors, which are doped to produce a deficit of electrons. Charges enter a transistor through its source terminal, travel down a channel, and exit out the drain terminal. In MOSFETs, if the the source and drain are made of p-type silicon, the channel will be made of n-type, and vice versa. The p-n junctions where these semiconductor types meet interrupt the flow of current . When a gate electrode applies voltage to the channel, current can flow across.

Each layer of a new kind of 3D contains so-called junctionless transistors. The bottom layer is made from silicon with excess mobile electrons, the top from silicon with excess holes. The transistors are linked together vertically to form complementary logic.Bao Lam, Yung Man Yu, et al.

In contrast, in junctionless transistors, the source, channel and drain are all completely either p-type or n-type, and so operate without p-n junctions. When a voltage is applied to the gates, they switch on, allowing current to flow. First proposed in 1925, they were not built until 2010 due to limits in fabrication technology; they require highly, uniformly doped channels at most about 10 nanometers thick.In MOSFETS, chipmakers use high heat to make sure dopants are located precisely where they are needed to be in the silicon crystal to create p-n junctions. Junctionless transistors don’t need these high temperatures. “Junctionless devices also use a simpler process flow, which can reduce costs and improve yield,” Cao says.

The new 3-D chips are made by laying down uniformly doped single-crystal silicon membranes each 10 nanometers or less thick using a wafer-scale roll-transfer-printing process. “Because the membranes are so thin and flexible, they conform to the underlying surface, avoiding the voids and warpage that often plague wafer bonding between rigid wafers,” Cao says.

The fact the nano-membranes can transfer onto surfaces that are not necessarily perfectly flat “is important because the current method typically used in industry requires sub-1-nanometer roughness for the surfaces to be bonded together and extremely flat—only a few microns of variations across the wafer,” says Veeresh Deshpande, an associate professor of electrical engineering at IIT Bombay, who did not participate in this study.. “The proposed method simplifies the process complexity and allows stacking several tiers of transistors, both for advanced computing and memory like DRAM.”

Cao and his colleagues fabricated three levels of junctionless transistors on a 75-millimeter silicon wafer, with each tier composed of 625 transistors over a 1,600-square-millimeter area. From these transistors they constructed a variety of logic gates and circuits—including inverters, NAND and NOR gates, and static random access memory (SRAM) cells—using vertical connections between the layers that were aligned with sub-10-nanometer accuracy.

The researchers were able to form circuits made up of transistors distributed over all three layers of the 3D chips. That led to a six-transistor SRAM cell with a footprint as little as one-third the size of its 2D layout.

A transistor’s switching speed depends on its current density, and the junctionless transistors showed a current density that could exceed 650 milliamperes per micrometer, which is comparable to older commercial silicon MOSFETs. More advanced MOSFETs do show current densities exceeding 1,000 milliamperes per micrometer, but Cao and his colleagues say that future engineering could further improve the performance of their devices.

“The key implication is that vertical stacking may not have to come with a severe transistor-performance penalty,” says Saptarshi Das, a professor of engineering science and mechanics at Pennsylvania State University, who did not take part in this research. “If scalable, this could open a practical path to denser, more energy-efficient chips with much shorter interconnects.”

Roll-transfer processes

The silicon wafers Cao’s team used are much smaller than the 300-mm ones most fabs use today. But transferring and stacking silicon membranes even across a 75 mm wafer without cracks, wrinkles, or defects “required a series of engineering innovations,” Cao says. These included adding surfactants during certain etching steps to reduce surface tension; adding polymer support layers for mechanical stability and surface protection; and adopting a roll-lamination process to apply uniform pressure during transfer.

“We began in 2019,” Cao says. “By 2024, we realized we had solved the fundamental barriers. The following year and a half was spent refining the process and demonstrating multilayered devices at wafer scale and 3D logic circuits.”

Beyond computing, integrating silicon with other materials in monolithic 3-D devices may open up new applications “that were previously out of reach.” Cao says. “For example, vertically stacking different types of single-crystalline semiconductors could enable ultra-sensitive X-ray detector panels or compact multispectral imaging systems.”

A new 3D chip has three layers of silicon transistors separated by about 90 nanometers of dielectric.Bao Lam, Yung Man Yu, et al.

One challenge monolithic devices will face is yield. “When you stack devices vertically, the traditional assumption is that every transistor in every layer must work perfectly, which can reduce overall chip yield,” Cao says. “We are working with circuit designers on defect-tolerant architectures that can absorb imperfections with minimal area and power overhead.”

Another hurdle is the way these 3D chips increase power density, concentrating heat. “We are collaborating with circuit and architecture teams on solutions such as dynamic voltage and frequency scaling and AI-assisted on-chip power regulation to actively manage heat,” Cao says.

Cao suggests the new approach is initially only promising for research and low-volume prototyping applications. “Once the benefits of monolithic 3D integration are clearly established, we can work toward high-volume manufacturing,” Cao says. “We simply want to be realistic and avoid over-claiming before the technology has been validated in those settings with full cost analysis.”

The scientists now want to partner with semiconductor foundries to demonstrate and refine the technology in a manufacturing environment, Cao says. Ultimately, “because our approach is silicon-based and compatible with foundry processes, it has a realistic path to adoption,” he notes. “It will be especially valuable for AI workloads that are increasingly limited by communication bottlenecks, which is directly addressed by this technology by bringing compute layers physically closer together.”

Cao and his colleagues detailed

in the 28 May

.