Future Transistor Stacking Plans Start to Diverge

Chipmakers agree that the transistor of the next decade will actually be two transistors stacked atop one another, packing in many more devices in the same area of silicon and leading to circuits that are as little as half the size of today’s. But their research efforts are beginning to show some important divergence in the details. Commercial introduction is likely six years away, so they are far from a final version, but research presented last week at IEEE VLSI Symposium in Honolulu and detailed today by IBM points toward two main paths.

Though companies have different names for it, in research this future device is commonly called the CFET, for complementary field effect transistor. It takes the two types of transistor, the p-channel and n-channel field effect transistor (PFET and NFET), that make up complementary metal-oxide semiconductor (CMOS) logic and stacks them instead of placing them side by side. Specifically, it stacks a type of transistor only recently commercially introduced called nanosheet or gate-all-around. This architecture itself contains a stack of nanometers-thick silicon sheets through which current flows. These are surrounded by a several atoms-thin layer of insulation and a carefully-concocted mix of metals collectively called the gate stack. The device is completed by caps of crystalline silicon at each end, the source and drain.

To construct CFETs, Intel, Samsung, and TSMC are pursuing a scheme called a monolithic process. Fundamentally that means they are building both the top and bottom device at the same time, one directly above the other. IBM, in contrast, is committed to a scheme that’s generally called a sequential process, because it builds a complete layer of transistors before constructing another layer above it. What’s more, IBM’s plans call for the transistor pair to be slightly staggered rather than directly in line as the monolithic process produces.

Chipmakers are expecting big gains from CFETs, especially IBM. The company, which does not manufacture its own chips but develops chipmaking processes for others, says its version of the technology, called Nanostack, will deliver as much as a 50 percent performance boost, 70 percent efficiency improvement, and 40 percent shrink of a computer chip’s memory compared to today’s 2-nanometer-node chips. Nanostack “is not just a one-time innovation,” says Huiming Bu, IBM Semiconductors vice president of global R&D. “It is a new transistor platform that enables so many innovations to come.”

Sequential integration for CFETs

One of the biggest barriers that’s held back sequential processes is the scorching temperatures needed to make high-quality transistors. “The key tradeoff is that the lower FET tiers must withstand the full thermal budget of the tiers above it,” Nirmaan Shankar told engineers at IEEE VLSI Symposium.

This heat, which can reach in excess of 900 C and last for hours, can ultimately reduce the amount of current a transistor can deliver and make it more difficult to control at what voltage it should switch on or off at.

In earlier research IBM demonstrated a way for NFETs to survive such a process. At the VLSI Symposium, Shankar explained how researchers did the same for PFETs.

There’s still work to be done to improve the process, but it points to an even more transistor-dense future. “In theory this process can be continued for additional FET tiers,” said Shankar. The team calculates that a chip with four tiers of transistors would shrink circuits by 40 percent versus a two-tiered chip.

IBM’s other innovation is to slightly offset the two tiers of transistors. Staggering the NFET and PFET instead of directly stacking them might seem like it would take up more space, but according to IBM it will really result in smaller logic circuits and better transistors.

One of the biggest issues with CFETs, generally, is managing to make all the needed connections to both transistors in a very confined vertical space, experts say. For example, the top transistor might need to connect to power, which comes from interconnects below the stack, and a data signal from above the stack might need to contact the bottom transistor. Needing to route these connections around the sides of the transistor stack puts a limit on how closely CFETs can sit.

Staggering solves some of these by allowing more direct connections. “The front side of each transistor and the backside of each transistor can be contacted independently,” says Bo. The staggered design is fundamental to delivering Nanostack’s 40 percent shrink of memory circuits, he says.

Monolithic integration for CFETs

For all its advantages, sequential CFETs are not as straightforward as monolithic processes. “I think across the industry, the monolithic is the leading integration scheme,” says Myunghee Na, a CFET expert and vice president at Intel.

Monolithic schemes essentially take a somewhat taller stack of nanosheets and use the top set for one device and the bottom set for the other. The difficulty is modifying, separating, and squeezing in all the parts and connections, some of which are in the shadow of others. In solving these problems, chipmakers are experimenting with new kinds of connections and improving the performance of the devices.

Samsung reported the first 3-nanosheet PFET and 3-nanosheet NFET, but Intel and TSMC have been working with 2-by-2 structures. For Intel, it’s a compromise between the transistor being able to switch faster with more sheets and the stack being so tall that its structures lead to too much signal-sapping capacitance, eating up power, Jami Wiedemer, a device engineer at Intel, explained to engineers at IEEE VLSI Symposium. But even that configuration “will likely change as the technology matures,” she said.

The companies are also modifying the electrical characteristics of the devices in other ways. Today, to serve applications that range from low-power mobile chips to high-clock-rate server CPUs, foundries offer versions of the same transistor that differ only in how much voltage is needed to turn them on or off. TSMC managed to make CFETs where those voltages could be set to three different levels for both the top and bottom device.

Intel, for its part, uses a different crystal orientation of silicon for the top and bottom transistor, because one orientation makes faster PFETs and the other makes faster NFETs. It’s done by growing the silicon for the two devices on separate wafers and then bonding the two wafers.

That process lends itself to a way of electrically isolating the top and bottom transistors that both Intel and TSMC use, forming a “middle dielectric isolation” layer from the insulating interface between the two wafers.

Samsung does it differently: Relying on an optimized crystal growth method, it starts with extra nanosheets between those nanosheets that will form the top and bottom devices. It then etches away the extras and fills in the gap with dielectric material.

Chipmakers are also using different methods to connect the top and bottom parts of the CFET. TSMC does this using a vertical connection along the side of the source and drain of the two devices. Intel’s “intraconnect” is formed completely within the CFET between the source and drain, and Samsung’s is built by cleaving through the source of the top transistor to link both devices to metal lines above them.

Expect chipmakers to try many more variations as they approach a commercially manufacturable CFET. “This is the ultimate architecture,” says Intel’s Na. It will take the whole industry, including semiconductor manufacturing equipment makers and electronic design automation software vendors, she says. “There is still a lot of work cut out for us, but it’s a really exciting time.”